1. Field of the Invention
This invention relates to a thin film transistor array substrate, and more particularly to a thin film transistor array substrate and a fabricating method thereof that are adaptive for protecting a thin film transistor without a protective film as well as reducing a manufacturing cost.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. The LCD drives a liquid crystal by an electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on upper and lower substrates.
The LCD includes a thin film transistor array substrate (lower array substrate) and a color filter array substrate (upper array substrate) that are joined in opposition to each other, a spacer for constantly keeping a cell gap between the two array substrates, and a liquid crystal filled in the cell gap.
The thin film transistor array substrate is comprised of a plurality of signal wirings and thin film transistors, and an alignment film coated thereon that provides an initial alignment of the liquid crystal. The color filter array substrate is comprised of a color filter for implementing color, a black matrix for preventing light leakage, and an alignment film coated thereon that provides an initial alignment of the liquid crystal.
In such an LCD, the thin film transistor array substrate has a complicated fabrication process, which causes a large rise in manufacturing cost of the liquid crystal display panel because it involves a semiconductor process and uses a plurality of mask processes. In order to solve this, the thin film transistor array substrate has been developed toward a reduction in the number of mask processes. This is because one mask process includes a number of individual processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, a four mask process has been used to fabricate the thin film transistor rather than the standard five mask process.
FIG. 1 is a plan view illustrating a lower transistor array substrate adopting a related art four-round mask process, and FIG. 2 is a section view of the thin film transistor array substrate taken along the II-II′ line in FIG. 1.
Referring to FIG. 1 and FIG. 2, a thin film transistor array substrate of a related art liquid crystal display panel includes a gate line 2 and a data line 4 provided on a lower substrate 1 in such a manner to intersect each other with having a gate insulating film 12 therebetween, a thin film transistor 30 provided at each intersection, a pixel electrode 22 provided at a cell area defined by the intersection structure, a storage capacitor 40 provided at an overlapping portion between the gate line 2 and a storage electrode 28, a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.
The gate line 2 for applying a gate signal and the data line 4 for applying a data signal are provided at an intersection structure to thereby define a pixel area 5.
The thin film transistor 30 allows a pixel signal on the data line 4 to be charged into the pixel electrode 22 and kept in response to a gate signal on the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. Further, the thin film transistor 30 includes an active layer 14 overlapping with the gate electrode 6 with a gate insulating film 12 therebetween to define a channel between the source electrode 8 and the drain electrode 10.
The active layer 14 also overlaps with the data line 4, a lower data pad electrode 62 and a storage electrode 28. On the active layer 14, an ohmic contract layer for making contact with the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62 and the storage electrode 28 is further provided.
The pixel electrode 22 is connected, via a first contact hole 20 passing through a protective film 18, to the drain electrode 10 of the thin film transistor 30, and is provided at a pixel area 5.
Thus, an electric field is formed between the pixel electrode 22 to which a pixel signal is supplied via the thin film transistor 30 and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate are rotated by the electric field due to dielectric anisotropy. Transmittance of light through the pixel area 5 is differentiated depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 40 consists of the gate line 2, and a storage electrode 28 overlapping with the gate line 2 with having the gate insulating film 12, the active layer 14 and the ohmic contact layer 16 therebetween. Herein, the storage electrode 28 is connected, via a second contact hole 42 defined at the protective film 18, to the pixel electrode 22. The storage capacitor 40 allows a pixel signal charged in the pixel electrode 22 to be stably maintained until the next pixel signal is charged.
The gate pad 50 is connected to a gate driver (not shown) to apply a gate signal to the gate line 2. The gate pad 50 consists of a lower gate pad electrode 52 extended from the gate line 2, and an upper gate pad electrode 54 connected, via a third contact hole 56 passing through the gate insulating film 12 and the protective film 18, to the lower gate pad electrode 52.
The data pad 60 is connected to a data driver (not shown) to apply a data signal to the data line 4. The data pad 60 consists of a lower data pad electrode 62 extended from the data line 4, and an upper data pad electrode 64 connected, via a fourth contact hole 66 passing through the protective film 18, to an upper data pad electrode 64 connected to the lower data pad electrode 62.
Hereinafter, a method of fabricating the thin film transistor array substrate of the liquid crystal display panel having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D.
Referring to FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 6 and the lower gate pad electrode 52 are provided on the lower substrate 1 by the first mask process.
More specifically, a gate metal layer is formed on the lower substrate 1 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and etching using a first mask to thereby form the first conductive pattern group including the gate line 2, the gate electrode 6 and the lower gate pad electrode 52. The gate metal layer is made from an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 12 is coated onto the lower substrate 1 provided with the first conductive pattern group. Further, semiconductor patterns including the active layer 14 and the ohmic contact layer 16; and a second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62 and the storage electrode 28 are formed on the gate insulating film 12 by the second mask process.
More specifically, the gate insulating film 12, an amorphous silicon layer, a n+ amorphous silicon layer and a data metal layer are sequentially provided on the lower substrate 1 provided with the first conductive pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 12 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The data metal layer is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the data metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion.
Subsequently, the data metal layer is patterned by wet etching using the photo-resist pattern to thereby provide the second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10 being integral to the source electrode 8 and the storage electrode 28.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 14 and the active layer 16.
The photo-resist pattern having a relatively low height is removed from the channel portion by ashing and thereafter the data metal layer and the ohmic contact layer 16 of the channel portion are etched by dry etching. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 8 from the drain electrode 10.
Then, the photo-resist pattern left on the second conductive pattern group is removed by stripping.
Referring to FIG. 3C, the protective film 18 including the first to fourth contact holes 20, 42, 56 and 66 are formed on the gate insulating film 12 provided with the second conductive pattern group.
More specifically, the protective film 18 is entirely formed on the gate insulating film 12 provided with the data patterns by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 18 is patterned by photolithography and etching using a third mask to thereby define the first to fourth contact holes 20, 42, 56 and 66. The first contact hole 20 passes through the protective film 18 to expose the drain electrode 10, whereas the second contact hole 42 passes through the protective film 18 to expose the storage electrode 28. The third contact hole 56 passes through the protective film 18 and the gate insulating film 12 to expose the lower gate pad electrode 52, whereas the fourth contact hole 66 passes through the protective film 18 to expose the lower data pad electrode 62. Herein, when a metal having a large dry etching ratio, such as molybdenum (Mo), is used as the data metal, the first, second and fourth contact holes 20, 42 and 66 pass through the drain electrode 10, the storage electrode 28 and the lower data pad electrode 62, respectively, to thereby expose the side surfaces thereof.
The protective film 18 is made from an inorganic insulating material identical to the gate insulating film 12, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, third conductive pattern group patterns including the pixel electrode 22, the upper gate pad electrode 54 and the upper data pad electrode 64 are provided on the protective film 18 by the fourth mask process.
More specifically, a transparent conductive film is coated onto the protective film 18 by a deposition technique such as sputtering, etc. Then, the transparent conductive film is patterned by photolithography and etching using a fourth mask to thereby provide the third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54 and the upper data pad electrode 64. The pixel electrode 22 is electrically connected, via the first contact hole 20, to the drain electrode 10 while being electrically connected, via the second contact hole 42, to the storage electrode 28. The upper gate pad electrode 54 is electrically connected, via the third contact hole 56, to the lower gate pad electrode 52. The upper data pad electrode 64 is electrically connected, via the fourth contact hole 66, to the lower data pad electrode 62.
Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO) or indium-zinc-oxide (IZO).
The related art thin film transistor array substrate is provided with the protective film 18 for protecting the thin film transistor 30. The protective film 18 is formed by depositing an inorganic insulating material using a PECVD device, or coating an organic insulating material using a spin coater or a spinless coater. Since formation of the protective film 18 uses the PECVD device, spin coater or spinless coater, the manufacturing cost rises.
Also, in the related art thin film transistor array substrate, the data line is often open. In this case, a separate process for repairing the data line is used.
Furthermore, in the related art thin film transistor array substrate, when the protective film 18 is formed from an organic insulating material, the pixel electrode 22 formed thereon is broken due to the protective film 18 being relatively thick. Particularly, the pixel electrode 22 is broken at the side surface of the protective film 18 exposed by a contact hole 20 for contacting the drain electrode 10 with the pixel electrode 22. Thus, since a pixel signal is not supplied via the drain electrode 10 to the pixel electrode 22, a spot defect occurs.
Moreover, in the related art thin film transistor array substrate, the storage capacitor 40 is comprised of the gate line 2 and the storage electrode 28 overlapping with each other with the gate insulating film 12, the active layer 14 and the ohmic contact layer 16 therebetween. In this case, a capacitance value of the storage capacitor 40 is reduced due to the gate insulating film 12, the active layer 14 and the ohmic contact layer 16 having a relatively large thickness for insulating the gate line 2 and the storage electrode 28. Also, a deterioration of picture quality such as a stain is generated due to a relatively low capacitance value of the storage capacitor 40.